/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2020. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef SVM_MASTER_DEV_CAPABILITY_H
#define SVM_MASTER_DEV_CAPABILITY_H

#include <linux/types.h>
#include "devmm_proc_info.h"
#include "devmm_channel.h"

void devmm_set_dev_mem_size_info(u32 did, struct devmm_chan_exchange_pginfo *info);
void devmm_clear_dev_mem_size_info(u32 devid);
int devmm_set_dev_capability(const u32 did, const u32 vfid, struct devmm_chan_exchange_pginfo *info);
void devmm_clear_dev_capability(const u32 did);

static inline bool devmm_dev_capability_support_dev_mem_map_host(u32 did)
{
    return devmm_svm->dev_capability[did].feature_dev_mem_map_host;
}

static inline bool devmm_dev_capability_support_pcie_th(u32 did)
{
    return devmm_svm->dev_capability[did].feature_pcie_th;
}

static inline bool devmm_dev_capability_support_bar_mem(u32 did)
{
    return devmm_svm->dev_capability[did].feature_bar_mem;
}

static inline bool devmm_dev_capability_support_bar_huge_mem(u32 did)
{
    return devmm_svm->dev_capability[did].feature_bar_huge_mem;
}

static inline bool devmm_dev_capability_support_read_only(u32 did)
{
    return devmm_svm->dev_capability[did].feature_dev_read_only;
}

static inline u64 devmm_dev_capability_dvpp_mem_size(u32 did)
{
    return devmm_svm->dev_capability[did].dvpp_memsize;
}

static inline bool devmm_dev_capability_support_offset_security(u32 did)
{
    return ((devmm_svm->dev_capability[did].feature_phycial_address & DEVMM_SUPPORT_OFFSET_SECURITY_MASK) ==
        DEVMM_SUPPORT_OFFSET_SECURITY_MASK);
}

static inline bool devmm_dev_capability_convert_support_offset(u32 did)
{
    return ((devmm_svm->dev_capability[did].feature_phycial_address & DEVMM_CONVERT_SUPPORT_OFFSET_MASK) ==
        DEVMM_CONVERT_SUPPORT_OFFSET_MASK);
}

static inline bool devmm_is_pcie_dma_support_sva(u32 dev_id)
{
    return devmm_svm->dev_capability[dev_id].feature_pcie_dma_support_sva;
}
#endif /* SVM_MASTER_DEV_CAPABILITY_H__ */
